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quad voltage monitor and sequencer adm1185 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features powered from 2.7 v to 5.5 v on the vcc pin monitors 4 supplies via 0.8% accurate comparators logical core with internal timeouts provides power supply sequencing and fault protection 4 inputs can be programmed to monitor different voltage levels with resistor dividers 3 open-drain enable outputs open-drain power-good output (pwrgd) 10-lead msop applications monitor and alarm functions power supply sequencing telecommunication and data communication equipment pc/servers functional block diagram vin1 ref = 0.6v out1 vin2 ref = 0.6v out2 vin3 ref = 0.6v out3 vin4 ref = 0.6v pwrgd gnd power and reference generator ref = 0.6v state machine core v c c adm1185 06196-001 figure 1. general description the adm1185 is an integrated, four-channel, voltage monitoring and sequencing device. a 2.7 v to 5.5 v power supply is required on the vcc pin to power the device. four precision comparators monitor four voltage rails. all comparators have a 0.6 v reference with a worst-case accuracy of 0.8%. resistor networks that are external to the vin1, vin2, vin3, and vin4 pins set the trip points for the monitored supply rails. a digital core interprets the status of the comparator outputs. internal time delays can be used for sequencing the startup of subsequent power supplies enabled by the outputs. supplies falling out of range are also detected and, as a result, appropriate outputs are disabled. the adm1185 has four open-drain outputs. in a typical configuration, out1 to out3 are used to enable power supplies, while pwrgd is a common power-good output indicating the status of all monitored supplies. the adm1185 is available in a 10-lead mini small outline package (msop). applications diagram 2.5v out 3.3v in 1.8v out 1.2v out 2.5v out 1.8v out 1.2v out out1 vin1 out2 vin2 out3 vin3 vin4 gnd pwrgd power good vcc adm1185 gnd regulator1 in en out gnd regulator2 in en out gnd regulator3 in en out 06196-002 figure 2.
adm1185 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 applications diagram ...................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 esd caution.................................................................................. 4 pin configuration and function descriptions..............................5 typical performance characteristics ..............................................6 theory of operation .........................................................................9 power-on sequencing and monitoring .....................................9 voltage monitoring after power-on ........................................ 10 cascading multiple devices...................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 3/07revision 0: initial version
adm1185 rev. 0 | page 3 of 16 specifications v cc = 2.7 v to 5.5 v, t a = ?40c to +85c. table 1. parameter min typ max unit conditions vcc pin operating voltage range, v cc 2.7 3.3 5.5 v supply current, i vcc 24 80 a vin1 to vin4 (vinx) pins input current, i vinleak ?20 +20 na v vinx = 0.7 v input rising threshold, v thr 0.5952 0.6000 0.6048 v out1 to out3 (outx), pwrgd pins output low voltage, v outl 0.4 v v cc = 2.7 v, i sink = 2 ma 0.4 v v cc = 1 v, i sink =100 a leakage current, i alert ?1 +1 a v cc that guarantees valid outputs 1 v all outputs are guaranteed to be either low or giving a valid output level from v cc = 1 v timing delays delays only applicable to certain operations states; refer to state diagram ( figure 19 ) for more details vin1 to out1 rising delay 100 190 280 ms v cc = 3.3 v, see figure 7 vin4 to pwrgd rising delay 100 190 280 ms v cc = 3.3 v, see figure 7 vin2 to out2, vin3 to out3 low-to-high propagation delay 30 s v cc = 3.3 v, see figure 9 high-to-low propagation delay, all inputs 30 s v cc = 3.3 v, see figure 10
adm1185 rev. 0 | page 4 of 16 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 2. parameter rating vcc pin ?0.3 v to +6 v vinx pins ?0.3 v to +6 v outx, pwrgd pins ?0.3 v to +6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature soldering (10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. thermal resistance package type ja unit 10-lead msop 137.5 c/w esd caution
adm1185 rev. 0 | page 5 of 16 pin configuration and fu nction descriptions gnd 1 v in1 2 v in2 3 v in3 4 v in4 5 vcc 10 out1 9 out2 8 out3 7 pwrgd 6 adm1185 top view (not to scale) 06196-003 figure 3. table 4. pin function descriptions pin o. nemonic description 1 gnd chip ground pin. 2 vin1 noninverting input of comparator 1. the voltage on this pin is compared with a 0.6 v reference. can be used to monitor a voltage rail via a resistor divider. the output of this comparator is monitored by the state machine core. this input can also be driven by a logic signal to initiate a power-up sequence. 3 vin2 noninverting input of comparator 2. the voltage on this pin is compared with a 0.6 v reference. can be used to monitor a voltage rail via a resistor divider. the output of this comparator is monitored by the state machine core. 4 vin3 noninverting input of comparator 3. the voltage on this pin is compared with a 0.6 v reference. can be used to monitor a voltage rail via a resistor divider. the output of this comparator is monitored by the state machine core. 5 vin4 noninverting input of comparator 4. the voltage on this pin is compared with a 0.6 v reference. can be used to monitor a voltage rail via a resistor divider. the output of this comparator is monitored by the state machine core. 6 pwrgd active-high, open-drain output. this output is pulled low once vcc = 1 v. when the voltage on each vinx input exceeds 0.6 v, the state machine moves from state4 to state5, and pwrgd is asserted. once in state 5 (the pwrgd state), this output is driven low if the volt age on vin1, vin2, vin3, or vin4 falls below 0.6 v. 7 out3 active-high, open-drain output. this output is pulled low once vcc = 1 v. when the voltage on vin3 exceeds 0.6 v, the state machine moves from state3 to state4, and out3 is asserted. once the power-up sequence is complete and state5 (the pwrgd state) is reac hed, this output is driven low if the voltage on vin1 falls below 0.6 v. 8 out2 active-high, open-drain output. this output is pulled low once vcc = 1 v. when the voltage on vin2 exceeds 0.6 v, the state machine moves from state2 to state3, and out2 is asserted. once the power-up sequence is complete and state5 (the pwrgd state) is reac hed, this output is driven low if the voltage on vin1 falls below 0.6 v. 9 out1 active-high, open-drain output. this output is pulled low once vcc = 1 v. when the voltage on vin1 exceeds 0.6 v, the state machine moves from state1 to state2, and out1 is asserted. a time delay of 190 ms (typical) is included before the assertion of this pin. once the power-up se quence is complete and state5 (the pwrgd state) is reached, this output is driven low if the voltage on vin1 falls below 0.6 v. 10 vcc positive supply input pin. the operating supply voltage range is 2.7 v to 5.5 v.
adm1185 rev. 0 | page 6 of 16 5.04.54.03.53.02.52.0 1.5 1.00.5 supply current (a) supply voltage (v) typical performance characteristics 50 0 5 10 15 20 25 30 35 40 45 05 . 5 280 260 240 220 200 180 160 140 120 2.7 5.55.35.14.94.74.54.3 4.1 3.9 3.5 3.7 3.33.1 2.9 delay (ms) voltage (v) vin4 to pwrgd delay 100mv overdrive vin1 to out1 delay 06196-004 06196-012 figure 4. supply current vs. supply voltage 50 0 5 10 15 20 25 30 35 40 45 ?40 90 70 80 605040302010 0 ?10?20?30 supply current (a) temperature (c) vcc = 2.7v vcc = 3.3v vcc = 5v 06196-005 figure 5. supply current vs. temperature 280 260 240 220 200 180 160 140 120 ?40 ?30 ?20 ?10 0 90 80 70605040302010 delay (ms) temperature (c) vin1 to out1 delay vin4 to pwrgd delay 06196-011 vcc = 3.3v, 100mv overdrive figure 6. vin1/vin4 to out1/pwrgd rising delay vs. temperature figure 7. vin1/vin4 to out1/pwrgd rising delay vs. supply voltage 50 45 40 35 30 25 20 15 10 5 0 ?40 90 80 706050403020 010 ?10?20?30 delay (s) temperature (c) vin3 to out3 delay vin2 to out2 delay 06196-013 vcc = 3.3v, 100mv overdrive figure 8. vin2/vin3 to out2/out3 rising delay vs. temperature 50 45 40 35 30 25 20 15 10 5 0 2.7 5.5 5.1 5.3 4.94.74.54.3 4.1 3.9 3.5 3.7 3.33.1 2.9 delay (s) voltage (v) vin3 to out3 delay vin2 to out2 delay 06196-014 100mv overdrive figure 9. vin2/vin3 to out2/out3 rising delay vs. supply voltage
adm1185 rev. 0 | page 7 of 16 60 50 40 30 20 10 0 2.7 5.5 5.1 5.3 4.94.74.54.3 4.1 3.9 3.5 3.7 3.33.1 2.9 delay (s) voltage (v) 06196-016 100mv overdrive figure 10. vin1 to out1 falling delay vs. supply voltage (100 mv overdrive) 50 40 30 20 10 0 ?40?30?20?100 102030405060708090 delay (s) temperature (c) 06196-015 vcc = 3.3v, 100mv overdrive figure 11. vinx to output fa lling delay vs. temperature 0.610 0.590 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 ?40 90 70 80 605040302010 0 ?10?20?30 vinx trip threshold (v) temperature (c) 06196-006 figure 12. vinx trip threshold vs. temperature 180 160 140 120 100 80 60 40 20 0 01 90 70 80 605040302010 maximum transient duration (s) overdrive (mv) 0 0 06196-007 figure 13. trip threshold maximum transient duration vs. input overdrive 200 180 160 140 120 100 80 60 40 20 0 0 102030405060708090100 delay (s) overdrive (mv) 06196-017 applicable only to channel 2 and channel 3 figure 14. propagation delay vs. input overdrive 400 350 300 250 200 150 100 50 0 02 222018161412 10 8642 output low voltage (mv) output sink current (ma) 4 06196-018 figure 15. output low voltage vs. output sink current
adm1185 rev. 0 | page 8 of 16 100 90 80 70 60 50 40 30 20 10 0 1.0 5.55.04.54.03.53.0 2.5 2.01.5 output low voltage (mv) supply voltage (v) 06196-019 1ma sink 100a sink figure 16. output low voltage vs. supply voltage
adm1185 rev. 0 | page 9 of 16 theory of operation the operation of the adm1185 is explained in this section in the context of the device in a voltage monitoring and sequencing application (see figure 18 ). in this application, the adm1185 monitors four separate voltage rails, turns on three regulators in a predefined sequence, and generates a power-good signal to turn on a controller when all power supplies are up and stable. power-on sequencing and monitoring the main supply, in this case 3.3 v, powers up the device via the vcc pin as the voltage rises. a supply voltage of 2.7 v to 5.5 v is needed to power the device. the vin1 pin monitors the main 3.3 v supply. an external resistor divider scales this voltage down for monitoring at the vin1 pin. the resistor ratio is chosen so that the vin1 voltage is 0.6 v when the main voltage rises to the preferred level at start- up (a voltage below the nominal 3.3 v level). r1 is 4.6 k and r2 is 1.2 k, so a voltage level of 2.9 v corresponds to 0.6 v on the noninverting input of the first comparator (see figure 17 ). vin1 1.2k ? 4.6k ? 0.6v to logic core adm1185 3.3v 2.9v 0v v t 2.9v supply gives 0.6v at vin1 pin 06196-020 figure 17. setting the undervoltage threshold with an external resistor divider out1 is an open-drain active high output. in this application, out1 is connected to the enable pin of a regulator. before the voltage on vin1 has reached 0.6 v, this output is switched to ground, disabling regulator 1. note that all outputs are driven to ground as long as there is 1 v on the vcc pin of the adm1185. when the main system voltage reaches 2.9 v, vin1 detects 0.6 v. this causes out1 to assert after a 190 ms (typical) delay. when this occurs, the open-drain output switches high, and the external pull-up resistor pulls the voltage on the regulator 1 enable pin above its turn-on threshold, turning on the output of regulator 1. the assertion of out1 turns on regulator 1. the 2.5 v output of this regulator begins to rise. this is detected by input vin2 (with a similar resistor divider scheme as shown in figure 18 ). when vin2 detects the 2.5 v rail rising above its uv point, it asserts output out2, which turns on regulator 2. a capacitor can be placed on the vin2 pin to slow the rise of the voltage on this pin. this effectively sets a time delay between the 2.5 v rail powering up and the next enabled regulator. the same scheme is implemented with the other input and output pins. every rail that is turned on via an output pin, outx, is monitored via an input pin vin(x+1). the final comparator inside the vin4 pin detects the final supply turning on, which is 1.2 v in this case. the output pins, out1 to out3 are logically anded together to generate a system power-good signal (pwrgd). there is an internal 190 ms delay (typical) associated with the assertion of the pwrgd output. table 5 is a truth table that steps through the power-on sequence of the outputs. any associated internal time delays are also shown. 2.5v out 3.3v in 1.8v out 1.2v out 2.5v out 1.8v out 1.2v out out1 vin1 out2 vin2 out3 vin3 vin4 gnd pwrgd power good vcc adm1185 gnd regulator1 in en out gnd regulator2 in en out gnd regulator3 in en out 06196-021 figure 18. voltage monitoring an d sequencing appl ication diagram tale 5. truth tale state state name out1 out2 out3 out4 next event next state 1 reset 0 0 0 0 vin1 high for 190 ms out1 on 2 out1 on 1 0 0 0 vin1 and vin2 high for 30 s out1, out2 on 3 out1, out2 on 1 1 0 0 vin1 and vin3 high for 30 s out1, out2, out3 on 4 out1, out2, out3 on 1 1 1 0 all high for 190 ms power good 5 power good 1 1 1 1 vin2 , vin3, or vin4 low for 30 s out1, out2, out3 on
adm1185 rev. 0 | page 10 of 16 voltage monitoring after power-on once pwrgd is asserted, the logical core latches into a different mode of operation. during the initial power-up phase, each output directly depends on an input (for example, vin3 asserting causes out3 to assert). when power-up is complete, this function is redundant. once in the pwrgd state, the following behavior can be observed: ? if the main 3.3 v supply monitored via vin1 faults in the power-good state, the pwrgd output is deasserted to warn the downstream controller. all outputs (out1 to out3) are immediately turned off, disabling all locally generated supplies. ? if a supply monitored by vin2 to vin4 fails, the pwrgd output is deasserted to warn the controller, but the other outputs are not deasserted. figure 20 and figure 21 are waveforms that highlight the behavior of the adm1185 under various fault situations during normal operation (that is, in the mode of operation after pwrgd is asserted). state1 start vin1 = ok (delay = 190ms typ) state2 out1 on vin2 = ok state3 out1, out2 on vin3 = ok state4 out1, out2, out3 on vin4 = ok (delay = 100ms min) state5 pwrgd vin2. vin3. vin4 = fault vin1 = fault vin1 = fault vin1 = fault vin1 = fault 06196-022 figure 19. flow diagram highlightin g the different modes of operation of the logical core
adm1185 rev. 0 | page 11 of 16 vin1 out1 out2 out3 pwrgd v t (rising) t prop 190ms 190ms notes 1. the rising threshold on the vin1 to vin4 pins is slightly higher than 0.6v as there is hysteresis on this pin. 06196-023 figure 20. power-up waveforms vin1 v t (falling) = 0.6v v t (rising) out1 out2 out3 pwrgd notes 1. the rising threshold on the vin1 to vin4 pins is slightly higher than 0.6v as there is hysteresis on this pin. t prop t prop 190ms 190ms 06196-024 figure 21. waveforms showing reaction to a temporary low glitch on the main supply 06196-029 ch1 1.00v ch2 1.00v ch3 1.00v ch4 1.00v m50.0ms ch1 380mv 1 2 3 4 out1 out2 out3 pwrgd figure 22. plot of out1, out2, out3, and pwrgd outputs at startup in an application similar to that shown in figure 18
adm1185 rev. 0 | page 12 of 16 cascading multiple devices multiple adm1185 devices can be cascaded in situations where a large number of supplies must be monitored and/or sequenced. the re are numerous configurations for interconnecting devices. the most suitable configuration depends on the application. figure 23 and figure 24 show two methods for cascading multiple adm1185 devices. vin1 vin2 vin3 vin4 3.3v 3.3 v v1 v2 v3 v1 v2 v3 gnd pwrgd vcc adm1185-a out1 out2 out3 3.3 v en1 regulator1 en2 regulator2 en3 regulator3 vin1 vin2 vin3 vin4 3.3v v4 v5 v6 v4 v5 v6 power good gnd pwrgd vcc adm1185-b out1 out2 out3 en4 regulator4 en5 regulator5 en6 regulator6 supplies scaled down with resistor dividers supplies scaled down with resistor dividers 06196-026 figure 23. cascading multiple adm1185 devices, option 1 vin1 vin2 vin3 vin4 3.3v 3.3 v v1 v2 3.3v v1 v2 v3 gnd pwrgd vcc adm1185-a out1 out2 out3 3.3 v en1 regulator1 en2 regulator2 en3 regulator3 vin1 vin2 vin3 vin4 3.3v v4 v3 v5 v6 v4 v5 v6 power good gnd pwrgd vcc adm1185-b out1 out2 out3 en4 regulator4 en5 regulator5 en6 regulator6 supplies scaled down with resistor dividers supplies scaled down with resistor dividers 06196-027 figure 24. cascading multiple adm1185 devices, option 2
adm1185 rev. 0 | page 13 of 16 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 25. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range package description package option branding adm1185armz-1 1 ?40c to +85c 10-lead mini small outline package [msop] rm-10 m9w ADM1185ARMZ-1REEL7 1 ?40c to +85c 10-lead mini small outline package [msop] rm-10 m9w 1 z = rohs compliant part.
adm1185 rev. 0 | page 14 of 16 notes
adm1185 rev. 0 | page 15 of 16 notes
adm1185 rev. 0 | page 16 of 16 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06196-0-3/07(0)

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